Dynamic random access memory (“DRAM”) is a type of random access memory that stores each bit of data in a separate capacitor. As real-world capacitors are not ideal and hence leak electrons, the information stored in the DRAM eventually fades unless the capacitor charge is periodically refreshed. In a multi-channel memory controller, this periodic refresh is accomplished by dedicating some portion of the read/write cycle to refreshing the DRAM. Typically, the overhead required for this refresh is approximately 1% of the peak bandwidth. Since most DRAMs are run below their peak bandwidth, for example, approximately 80%, this refresh overhead does not represent a significant portion of the read/write cycle. However, as the DRAM is run at higher percentages of peak bandwidth, for example, approximately 95%, the time dedicated to refresh overhead becomes increasingly more expensive.